Serial Rfu Enable Register_0 And 2 (Scidter_0 And Scidter_2) - Renesas H8S/2158 User Manual

Section 16 Serial Communication Interface (SCI, IrDA, and CRC)

16.3.12 Serial RFU Enable Register_0 and 2 (SCIDTER_0 and SCIDTER_2)

SCIDTER_0 and SCIDTER_2 enable or disable the RFU activation requests by SCI_0 and SCI_2,
respectively.
Bit Bit Name
7 TDRE_DTE
6 RDRF_DTE
5 to —
0
Rev. 3.00 Jan 25, 2006 page 416 of 872
REJ09B0286-0300
Initial
Value R/W Description
0 R/W TERE Data Transfer Enable
Enables/disables the RFU to be activated by TDRE = 1.
•
•
0 R/W RDRF Data Transfer Enable
Enables/disables activation of the RFU by RDRF = 1 in
SSR.
0: Disables activation of the RFU, and does not mask the
RXI interrupt request
1: Enables activation of the RFU, and masks the RXI
interrupt request
[Clearing condition]
When data transfer has been completed by the RFU
activated by RDRF = 1 in SSR (FIFO FULL)
All 0 R Reserved
These bits are always read as 0 and cannot be modified.
SMIF = 0 in SCMR, or SMIF = 1 and BLK = 1 in SMR
0: Disables activation of the RFU by TDRE = 1 in
SSR, and does not mask the TXI interrupt request
1: Enables activation of the RFU by TDRE = 1 in SSR,
and masks the TXI interrupt request
[Clearing condition]
When data transfer has been completed by activation
of the RFU by TDRE = 1 (FIFO EMPTY)
SMIF = 1 in SCMR and BLK = 1 in SMR
0: Disables activation of the RFU by TEND = 1 in
SSR, and does not mask the TXI interrupt request
1: Enables activation of the RFU by TEND = 1 in SSR,
and masks the TXI interrupt request
[Clearing condition]
When data transfer has been completed by the RFU
activation by TEND = 1 in SSR