Renesas H8S/2158 User Manual page 46

Figure 26.9 Processing for X1 and X2 Pins ............................................................................. 769
Section 27 Power-Down Modes
Figure 27.1 Mode Transition Diagram..................................................................................... 779
Figure 27.2 Medium-Speed Mode Timing............................................................................... 782
Figure 27.3 Software Standby Mode Application Example..................................................... 784
Figure 27.4 Hardware Standby Mode Timing.......................................................................... 785
Section 29 Electrical Characteristics
Figure 29.1 Darlington Transistor Drive Circuit (Example) .................................................... 833
Figure 29.2 LED Drive Circuit (Example)............................................................................... 833
Figure 29.3 Output Load Circuit .............................................................................................. 834
Figure 29.4 System Clock Timing ........................................................................................... 835
Figure 29.5 Oscillation Stabilization Timing ........................................................................... 836
Figure 29.6 Oscillation Stabilization Timing (Exiting Software Standby Mode) .................... 836
Figure 29.7 Reset Input Timing ............................................................................................... 838
Figure 29.8 Interrupt Input Timing .......................................................................................... 838
Figure 29.9 Basic Bus Timing/2-State Access......................................................................... 840
Figure 29.10 Basic Bus Timing/3-State Access......................................................................... 841
Figure 29.11 Basic Bus Timing/3-State Access with One Wait State........................................ 842
Figure 29.12 CF Interface Basic Timing/3-State Access ........................................................... 843
Figure 29.13 Burst ROM Access Timing/2-State Access .......................................................... 844
Figure 29.14 Burst ROM Access Timing/1-State Access .......................................................... 845
Figure 29.15 I/O Port Input/Output Timing ............................................................................... 847
Figure 29.16 FRT Input/Output Timing..................................................................................... 847
Figure 29.17 FRT Clock Input Timing ...................................................................................... 847
Figure 29.18 8-Bit Timer Output Timing................................................................................... 848
Figure 29.19 8-Bit Timer Clock Input Timing........................................................................... 848
Figure 29.20 8-Bit Timer Reset Input Timing ........................................................................... 848
Figure 29.21 PWM, PWMX Output Timing.............................................................................. 848
Figure 29.22 SCK Clock Input Timing...................................................................................... 849
Figure 29.23 SCI Input/Output Timing (Clock Synchronous Mode)......................................... 849
Figure 29.24 A/D Converter External Trigger Input Timing ..................................................... 849
Figure 29.25 WDT Output Timing (RESO)............................................................................... 849
2
Figure 29.26 I C Bus Interface Input/Output Timing ................................................................ 851
Figure 29.27 USB Driver/Receiver Output Timing ................................................................... 852
Figure 29.28 Multimedia Card Interface Timing ....................................................................... 853
Figure 29.29 H-UDI ETCK Timing........................................................................................... 854
Figure 29.30 Reset Hold Timing................................................................................................ 855
Figure 29.31 H-UDI Input/Output Timing................................................................................. 855
Rev. 3.00 Jan 25, 2006 page xliv of lii