Serial Status Register (Ssr) - Renesas H8S/2158 User Manual

Section 16 Serial Communication Interface (SCI, IrDA, and CRC)
Bit Functions in Smart Card Interface Mode (When SMIF in SCMR = 1)
Bit Bit Name
7 TIE
6 RIE
5 TE
4 RE
3 MPIE
2 TEIE
1 CKE1
0 CKE0
Legend:
X: Don't care
16.3.7

Serial Status Register (SSR)

SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. TDRE,
RDRF, ORER, PER, and FER can only be cleared. Some bits in SSR have different functions in
normal mode and smart card interface mode.
Rev. 3.00 Jan 25, 2006 page 398 of 872
REJ09B0286-0300
Initial Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Description
Transmit Interrupt Enable
When this bit is set to 1,a TXI interrupt request is
enabled.
Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt
requests are enabled.
Transmit Enable
When this bit is set to 1, transmission is enabled.
Receive Enable
When this bit is set to 1, reception is enabled.
Multiprocessor Interrupt Enable (enabled only when
the MP bit in SMR is 1 in asynchronous mode)
Write 0 to this bit in smart card interface mode.
Transmit End Interrupt Enable
Write 0 to this bit in smart card interface mode.
Clock Enable 1,0
Controls the clock output from the SCK pin. In GSM
mode, clock output can be dynamically switched.
For details, see section 16.7.8, Clock Output
Control.
When GM in SMR = 0
00: Output disabled (SCK pin functions as I/O port.)
01: Clock output
1X: Reserved
When GM in SMR = 1
00: Output fixed to low
01: Clock output
10: Output fixed to high
11: Clock output