Clock Timing; Figure 29.4 System Clock Timing; Table 29.7 Clock Timing - Renesas H8S/2158 User Manual

29.3.1

Clock Timing

Table 29.7 shows the clock timing. The clock timing specified here covers clock output (φ), clock
pulse generator (crystal) and external clock input (EXTAL pin) oscillation stabilization times. For
details of external clock input (EXTAL pin and EXCL pin) timing, see section 26, Clock Pulse
Generator.

Table 29.7 Clock Timing

Condition A: V = 3.0 V to 3.6 V, V
CC
Condition B: V = 2.7 V to 3.6 V, V
CC
Item
Clock cycle time
Clock high pulse width
Clock low pulse width
Clock rise time
Clock fall time
Reset oscillation
stabilization (crystal)
Software standby
oscillation stabilization
time (crystal)
External clock output
stabilization delay time
The clock timing is shown below.
= 0 V, φ = 5 MHz to 25 MHz
SS
= 0 V, φ = 5 MHz to 20 MHz
SS
Condition A
Symbol Min Max
t 40 200
cyc
t 15 —
CH
t 15 —
CL
t — 5
Cr
t — 5
Cf
t 10 —
OSC1
t 8 —
OSC2
t 500 —
DEXT
t
CH
φ

Figure 29.4 System Clock Timing

Section 29 Electrical Characteristics
Condition B
Min Max
50 200
20 —
20 —
— 5
— 5
10 —
8 —
500 —
t
cyc
t
Cf
t
t
Cr
CL
Rev. 3.00 Jan 25, 2006 page 835 of 872
Unit Reference
ns Figure 29.4
ms Figure 29.5
Figure 29.6
µs Figure 29.5
REJ09B0286-0300