Table of Contents
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Section 1 Overview
Type
Symbol
WAIT
Bus
control
RD
HWR
LWR
AS/IOS
CS256
Interrupts
NMI
IRQ15 to
IRQ0
ExIRQ15 to
ExIRQ2
ETRST
On-chip
emulator
ETMS
ETDO
ETDI
ETCK
Rev. 3.00 Jan 25, 2006 page 10 of 872
REJ09B0286-0300
Pin No.
TBP-112A
I/O
G2
Input
H3
Output
G4
Output
J3
Output
H1
Output
G2
Output
D1
Input
J1, H2
Input
J9, L10
B3, C4
F1, F2
H11, H10
H9, J11
J10, H8
K11, K10
A9, C8
D6, A5
A3, B4
D5, A4
H7, L8
J7, K7
L7, H6
F3
Input
E9
Input
D11
Output
L3
Input
J4
Input
Name and Function
Requests insertion of a wait state in the
bus cycle when accessing an external 3-
state address space.
This pin is low when the external
address space is being read from.
This pin is low when the external
address space is being written to, and
the upper half of the data bus is enabled.
This pin is low when the external space
is being written to, and the lower half of
the data bus is enabled.
This pin is low when address output on
the address bus is valid.
Indicates that the 256-kbyte area from
H'F80000 to H'FBFFFF is accessed.
Nonmaskable interrupt request input pin
These pins request a maskable interrupt.
Selectable to which pin of IRQn or
ExIRQn to insert IRQ15 to IRQ0
interrupts.
On-chip emulator interface pins
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