Figure 14.7 Fall Modification And Ihi Synchronization Timing Chart; Table 14.8 Examples Of Tcr, Tcsr, And Tcorb Settings - Renesas H8S/2158 User Manual

16-bit single-chip microcomputer h8s family/h8s/2100 series
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Section 14 Timer Connection

Table 14.8 Examples of TCR, TCSR, and TCORB Settings

Register
Bit
TCR in
7
TMR_1
6
5
4, 3
2 to 0
TCSR in
3 to 0
TMR_1
TCORB
in TMR_1
IHI signal
IVI signal (PDC signal)
IVO signal
(without fall modification,
with IHI synchronization)
IVO signal
(with fall modification,
without IHI synchronization)
IVO signal
(with fall modification
and IHI synchronization)

Figure 14.7 Fall Modification and IHI Synchronization Timing Chart

Rev. 3.00 Jan 25, 2006 page 366 of 872
REJ09B0286-0300
Abbreviation
Contents
CMIEB
0
CMIEA
0
OVIE
0
CCLR1,
11
CCLR0
CKS2 to CKS0
101
OS3 to OS0
0011
1001
H'03
(example)
Description
Interrupts due to compare-match and
overflow are disabled
TCNT is cleared by the rising edge of the
external reset signal (inverse of the IVI
signal)
TCNT is incremented on the rising edge
of the external clock (IHI signal)
Not changed by compare-match B;
output inverted by compare-match A
(toggle output)
When TCORB < TCORA, 1 output on
compare-match B, 0 output on compare-
match A
Compare-match on the 4th (example)
rise of the IHI signal after the rise of the
inverse of the IVI signal
3
2
1
TCNT
0
5
4
TCNT = TCORB (3)

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