Timing Of On-Chip Supporting Modules; Table 21.6 Timing Of On-Chip Supporting Modules - Renesas H8S Series Hardware Manual

21.3.3

Timing of On-Chip Supporting Modules

Table 21.6 lists the timing of on-chip supporting modules.

Table 21.6 Timing of On-Chip Supporting Modules

Conditions: V = 4.5 V to 5.5 V, AV
CC
T = –20°C to +75°C (regular specifications), T
a
specifications)
Item
I/O port Output data delay
time
Input data setup time t
Input data hold time
TPU Timer output delay
time
Timer input setup time t
Timer clock input
setup time
Timer
clock
pulse
width
SCI Input
clock
cycle
Input clock pulse
width
Input clock rise time
Input clock fall time
Transmit data delay
time
Receive data setup
time (synchronous)
Receive data hold
time (synchronous)
= 4.5 V to 5.5 V, V
CC
Symbol
t
PWD
PRS
t
PRH
t
TOCD
TICS
t
TCKS
Single t
TCKWH
edge
Both t
TCKWL
edges
Asynchro- t
Scyc
nous
Synchro-
nous
t
SCKW
t
SCKr
t
SCKf
t
TXD
t
RXS
t
RXH
Section 21 Electrical Characteristics
= AV
SS
= –40°C to +85°C (wide-range
a
Min. Max.
— 50
30 —
30 —
— 50
30 —
30 —
1.5 —
2.5 —
4 —
6 —
0.4 0.6
— 1.5
— 1.5
— 50
50 —
50 —
Rev. 6.00 Mar 15, 2006 page 515 of 570
= 0, φ = 4 MHz to 20 MHz,
SS
Unit Test Conditions
ns Figure 21.6
ns Figure 21.7
ns Figure 21.8
t
cyc
t Figure 21.9
cyc
t
Scyc
t
cyc
ns Figure 21.10
REJ09B0211-0600