Renesas H8S/2158 User Manual page 560

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Section 17 I C Bus Interface (IIC)
Bit Bit Name Initial Value
0 RDRF 0
Notes: 1. Only 0 can be written to clear the flag.
2. Address disagree in master mode or slave mode transmission.
3. Address (including general call address) match in master mode or slave mode
reception.
Rev. 3.00 Jan 25, 2006 page 506 of 872
REJ09B0286-0300
R/W Description
R Receive Data Register Full
0: Receive buffer (ICDRR) contains no receive data
1: Receive buffer (ICDRR) contains receive data; read
from ICDRR is possible
[Setting conditions]
•
When transmission of first frame (address + R/W = 1)
in master mode ends (rise of 9th clock)
•
When reception of second or subsequent frames
ends (fall of 8th clock) *
•
When ICDRX is read from with receive data in the
shift register (SDRF = 1) in receive mode
[Clearing conditions]
•
When ICDRX is read from with no receive data in the
shift register (SDRF = 0) in receive mode
•
When start condition is detected
This bit is enabled during reception by the IIC operation
reservation adapter.
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