Endpoint Data Registers 0S, 0O, 0I, 1, 2, And 3 (Epdr0S, Epdr0O, Epdr0I, Epdr1, Epdr2, And Epdr3) - Renesas H8S/2158 User Manual

18.3.3 Endpoint Data Registers 0S, 0O, 0I, 1, 2, and 3 (EPDR0S, EPDR0O, EPDR0I,
EPDR1, EPDR2, and EPDR3)
EPDRs intervene in the data transfer between the CPU and FIFOs in each host input transfer or
host output transfer for the USB function core endpoints 1 and 2. EPDR0I, EPDR1, and EPDR3
are write-only registers used for host input transfer. EPDR0S and EPDR0O are read-only registers
used for host output transfer. EPDR2 is specified depending on the transfer direction specified in
EPDIR0. If EPDIR0 is specified as a host input transfer, EPDR2 is specified as a read-only
register; if EPDIR0 is specified as a host output transfer, EPDR2 is specified as a write-only
register.
Data written in EPDR0I, EPDR1, EPDR2 (write-only register), and EPDR3 is stored in the FIFOs
and is enabled by setting the EPTE bit in PTTER0. This enabled data is transferred to the USB
function core according to the USB function core's request and then sent to the host.
Data sent to the host is stored in the FIFO by the USB function core and is enabled by returning an
ACK handshake after all bytes of data packet has been received. When reading EPDR0S,
EPDR0O, or EPDR2 (read-only register), data is stored in the FIFO and then enabled data is read
out in order of transfer.
EPDR is initialized to H'00 by a system reset or function software reset (see section 18.3.16, USB
Control Registers 0 and 1 (USBCR0, USBCR1)).
Note that EPDR for endpoints 4 and 5 is not supported. Data is handled by reading on-chip RAM
directly.
EPDR0S
Bit Bit Name Initial Value R/W
7 to D7 to D0 All 0
0
EPDR0O
Bit Bit Name Initial Value R/W
7 to D7 to D0 All 0
0
Section 18 Universal Serial Bus Interface (USB)
Description
R Endpoint 0 is used for input or output transfer and
EPDR0S is specified as a read-only register. EPDR0S
is a specific FIFO for setup command reception and is
enabled when the SETICNT bit in USBMDCR is set to
1. EPDR0S access is disabled when the SETICNT bit
is cleared to 0.
Description
R Endpoint 0 is used for input or output transfer and
EPDR0O is specified as a read-only register.
Rev. 3.00 Jan 25, 2006 page 559 of 872
REJ09B0286-0300