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Section 22 A/D Converter
22.5.2
Scan Mode
In scan mode, A/D conversion is to be performed sequentially on the specified channels (four
channels max.). Operations are as follows.
1. When the ADST bit in ADCSR is set to 1 by software or an external trigger input, A/D
conversion starts on the first channel in the group (CIN0 when the CH2 bit in ADCSR is 0
while the SCANE and KBADE bits in KBCOMP are B'11, or AN4 when the CH2 bit in
ADCSR is 1).
2. When A/D conversion for each channel is completed, the result is sequentially transferred to
the A/D data register corresponding to each channel.
3. When conversion of all the selected channels is completed, the ADF bit in ADCSR is set to 1.
If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends.
Conversion of the first channel in the group starts again.
4. The ADST bit is not automatically cleared to 0 so steps [2] to [3] are repeated as long as the
ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops.
22.5.3
Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (t
1, then starts A/D conversion. Figure 22.2 shows the A/D conversion timing. Table 22.4 indicates
the A/D conversion time.
As indicated in figure 22.2, the A/D conversion time (t
time (t
). The length of t
SPL
total conversion time therefore varies within the ranges indicated in table 22.4.
In scan mode, the values given in table 22.4 apply to the first conversion time. In the second and
subsequent conversions, the conversion time is 266 states (fixed) when CKS = 0 and 134 states
(fixed) when CKS = 1.
Rev. 3.00 Jan 25, 2006 page 706 of 872
REJ09B0286-0300
varies depending on the timing of the write access to ADCSR. The
D
) passes after the ADST bit in ADCSR is set to
D
) includes t
CONV
D
and the input sampling
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