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Section 12 16-Bit Free-Running Timer (FRT)
Figure 12.20 Conflict between OCR Write and Compare-Match
12.7.4
Switching of Internal Clock and FRC Operation
When the internal clock is changed, the changeover may cause FRC to increment. This depends on
the time at which the clock is switched (bits CKS1 and CKS0 are rewritten), as shown in table
12.3.
When an internal clock is used, the FRC clock is generated on detection of the falling edge of the
internal clock scaled from the system clock (φ). If the clock is changed when the old source is high
and the new source is low, as in case no. 3 in table 12.3, the changeover is regarded as a falling
edge that triggers the FRC clock, and FRC is incremented. Switching between an internal clock
and external clock can also cause FRC to increment.
Rev. 3.00 Jan 25, 2006 page 312 of 872
REJ09B0286-0300
φ
Address
Internal write signal
OCRAR (OCRAF)
Compare-match signal
FRC
OCR
Automatic addition is not performed
because compare-match signals are disabled.
(When Automatic Addition Function Is Used)
OCRAR (OCRAF)
address
Old data
New data
Disabled
N
N
N+1
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