Renesas H8S/2158 User Manual page 650

Section 18 Universal Serial Bus Interface (USB)
Bit Bit Name Initial Value R/W
7, 6 — All 0
5 PFSEL2 0
4 CKSEL2 0
3 CKSEL1 0
2 CKSEL0 0
1 PFSEL1 0
0 PFSEL0 1
Legend:
X: Don't care
Rev. 3.00 Jan 25, 2006 page 596 of 872
REJ09B0286-0300
Description
R Reserved
These bits are always read as 0 and cannot be modified.
R/W PLL Frequency Select 2
Combined with the PFSEL1 and PFSEL0 bits, this bit
selects the frequency of the clock to be provided to the
USB operating clock generation circuit (PLL).
For details, refer to the description of the PFSEL1 and
PFSEL0 bits.
R/W Clock Source Select 2 to 0
R/W These bits select the source of the clock to be provided
to the USB operating clock generation circuit (PLL).
R/W
0XX: PLL stops operation and no clock is input to the
PLL.
100: Setting prohibited
101: PLL stops operation and the USEXCL pin input (48
MHz) is directly used instead of PLL output.
110: PLL operates using the system clock generator
(XTAL) as a clock source.
111: PLL operates using the USEXCL pin input as a
clock source.
R/W PLL Frequency Select 1 and 0
R/W The PFSEL2 to PFSEL0 bits select the frequency of the
clock to be provided to the USB operating clock
generation circuit (PLL).
The PLL circuit generates a 48-MHz USB operating
clock based on the clock source whose frequency is
specified by the PFSEL1 and PFSEL2 bits.
000: PLL input clock frequency is 8 MHz
001: PLL input clock frequency is 12 MHz
010: PLL input clock frequency is 16 MHz
011: PLL input clock frequency is 20 MHz
100: PLL input clock frequency is 24 MHz
Other than above: Setting prohibited