Basic Operation Timing; Figure 6.5 Bus Timing For 8-Bit, 2-State Access Space - Renesas H8S/2158 User Manual

6.5.3

Basic Operation Timing

8-Bit, 2-State Access Space: Figure 6.5 shows the bus timing for an 8-bit, 2-state access space.
When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Wait
states cannot be inserted.
AS/IOS (IOSE = 1)
CS256 (CS256E = 1)
CPCS1 (CPCSE = 1 and CFE = 0)
AS/IOS * (IOSE = 0)
Read
Write
Note: * For external address space access, this signal is not output when the 256-kbyte expansion area
is accessed with CS256E = 1 and when the CP/CF expansion area is accessed with CPCSE = 1.

Figure 6.5 Bus Timing for 8-Bit, 2-State Access Space

φ
Address bus
RD
D15 to D8
D7 to D0
HWR
D15 to D8
Bus cycle
T T
1 2
Valid
Invalid
Valid
Rev. 3.00 Jan 25, 2006 page 125 of 872
Section 6 Bus Controller
REJ09B0286-0300