Timer Control/Status Register (Tcsr) - Renesas H8S/2158 User Manual

13.3.5

Timer Control/Status Register (TCSR)

TCSR indicates the status flags and controls compare-match output.
TCSR_0
Bit Bit Name Initial Value R/W
7 CMFB 0
6 CMFA 0
5 OVF 0
4 ADTE 0
Description
R/(W) * Compare-Match Flag B
[Setting condition]
•
When the values of TCNT_0 and TCORB_0 match
[Clearing condition]
•
Read CMFB when CMFB = 1, then write 0 in CMFB
R/(W) * Compare-Match Flag A
[Setting condition]
•
When the values of TCNT_0 and TCORA_0 match
[Clearing condition]
•
Read CMFA when CMFA = 1, then write 0 in CMFA
R/(W) * Timer Overflow Flag
[Setting condition]
•
When TCNT_0 overflows from H'FF to H'00
[Clearing condition]
•
Read OVF when OVF = 1, then write 0 in OVF
R/W A/D Trigger Enable
Enables or disables A/D converter start requests by
compare-match A.
0: A/D converter start requests by compare-match A are
disabled
1: A/D converter start requests by compare-match A are
enabled
Section 13 8-Bit Timer (TMR)
Rev. 3.00 Jan 25, 2006 page 323 of 872
REJ09B0286-0300