Figure 8.3 Example Of Rfu Response Time - Renesas H8S/2158 User Manual

Section 8 RAM-FIFO Unit (RFU)
• RFU bus cycle: 2 states
• Cycle to synchronize the RFU signal with the peripheral module clock: 1 and 2 states
(depending on the peripheral module clock)
The total of the above cycles is 5 to 13 states. Cycles for synchronization of the peripheral module
clock with the system clock are needed even when the hardware FIFO is used instead of the RFU.
Therefore, RAM-FIFO overhead by the RFU is 3 to 10 states (except for wait states for external
extension). To reduce the RFU response time, it is recommended to set the external extension area
access to 3 states/no waits.
CPU bus cycle
T1
φ
12-MHz clock
for the USB
SB0V * 1
2
SB1V *
RFU activation
request
RFU bus cycle
Notes: 1. USB SENDBUFCR SB0V bit: Transmit buffer 0 valid bit
2. USB SENDBUFCR SB1V bit: Transmit buffer 1 valid bit
Rev. 3.00 Jan 25, 2006 page 190 of 872
REJ09B0286-0300
CPU bus cycle
CPU bus cycle
T2 T1 T2
System clock Request output
synchronization cycle cycle

Figure 8.3 Example of RFU Response Time

RFU bus cycle
T1 T2 T1 T2
Cycle to wait RFU bus cycle
for the end of
the current
bus cycle
CPU bus cycle CPU bus cycle
T1 T2 T1
Synchronization System clock
cycle with synchronizatioin
the peripheral cycle
module clock
T2