Renesas H8S/2158 User Manual page 532

2
Section 17 I C Bus Interface (IIC)
ICDR can be written to and read from only when the ICE bit is set to 1 in ICCR. The initial value
of ICDR is undefined.
The ICDRE and ICDRF flags are set and cleared under the conditions shown below. Setting the
ICDRE and ICDRF flags affects the status of the interrupt flags.
Bit Bit Name Initial Value R/W
— ICDRE —
Rev. 3.00 Jan 25, 2006 page 478 of 872
REJ09B0286-0300
Description
— Transmit Data Register Empty
[Setting conditions]
•
When satisfaction of a start condition is detected in
the bus line state with the I
format selected
•
When data is transferred from the transmit buffer to
the shift register
(Data transfer from the transmit buffer to the shift
register if the shift register is empty when ICDRE = 0
in transmit mode)
(Do not write to ICDR in receive mode because the
ICDRE flag value is invalid)
[Clearing conditions]
•
When transmit data is written in ICDR (transmit
buffer) in transmit mode
•
When satisfaction of a stop condition is detected in
the bus line state with the I
format selected
If transmit data is written to ICDR (transmit buffer) in
transmit mode when ICDR does not contain data to
be transmitted, ICDRE is cleared to 0. However, since
data is transferred from the transmit buffer to the shift
register immediately, ICDRE is set to 1 again.
•
Internal state initialization
(Writing 0 to the TRS bit in ICCR during transfer is
valid after reception of a frame containing an
acknowledge bit)
2
C bus format or serial
2
C bus format or serial