Renesas H8S/2158 User Manual page 32

19.3.2 Command Type Register (CMDTYR)................................................................. 632
19.3.3 Response Type Register (RSPTYR) .................................................................... 633
19.3.4 Transfer Byte Number Count Register (TBCR) .................................................. 636
19.3.5 Transfer Block Number Counter (TBNCR)......................................................... 636
19.3.6 Command Registers 0 to 5 (CMDR0 to CMDR5) ............................................... 637
19.3.7 Response Registers 0 to 16, and D (RSPR0 to RSPR16, and RSPRD) ............... 638
19.3.8 Command Start Register (CMDSTRT)................................................................ 640
19.3.9 Operation Control Register (OPCR) .................................................................... 641
19.3.10 Command Timeout Control Register (CTOCR) .................................................. 643
19.3.11 Data Timeout Register (DTOUTR) ..................................................................... 644
19.3.12 Card Status Register (CSTR) ............................................................................... 645
19.3.13 Interrupt Control Registers 0, 1 (INTCR0, INTCR1) .......................................... 647
19.3.14 Interrupt Status Registers 0, 1 (INTSTR0, INTSTR1)......................................... 649
19.3.15 Pin Mode Control Register (IOMCR).................................................................. 653
19.3.16 Transfer Clock Control Register (CLKON)......................................................... 654
19.4 MCIF Activation ............................................................................................................... 655
19.4.1 Initial Status ......................................................................................................... 655
19.4.2 Activation Procedure ........................................................................................... 655
19.5 Operations in MMC Mode ................................................................................................ 656
19.5.1 Operation of Broadcast Commands ..................................................................... 656
19.5.2 Operation of Relative Address Commands.......................................................... 657
19.5.3 Operation of Commands Not Requiring Command Response............................. 657
19.5.4 Operation of Commands without Data Transfer .................................................. 659
19.5.5 Commands with Read Data.................................................................................. 663
19.5.6 Commands with Write Data................................................................................. 669
19.6 Operations in SPI Mode.................................................................................................... 675
19.6.1 Operation of Commands without Data Transfer .................................................. 675
19.6.2 Commands with Read Data.................................................................................. 679
19.6.3 Commands with Write Data................................................................................. 683
19.7 Interrupt Sources ............................................................................................................... 687
19.8 Usage Notes ...................................................................................................................... 687
Section 20 Encryption Operation Circuit (DES and GF)
Section 21 D/A Converter
21.1 Features ............................................................................................................................. 691
21.2 Input/Output Pins .............................................................................................................. 692
21.3 Register Descriptions ........................................................................................................ 692
21.3.1 D/A Data Registers 0 and 1 (DADR0, DADR1) ................................................. 692
21.3.2 D/A Control Register (DACR) ............................................................................ 692
21.4 Operation........................................................................................................................... 694
Rev. 3.00 Jan 25, 2006 page xxx of lii
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