Renesas H8S/2158 User Manual page 457

Bit Bit Name Initial Value
2 TEND 1
1 MPB 0
0 MPBT 0
Note: * Only 0 can be written, to clear the flag.
Section 16 Serial Communication Interface (SCI, IrDA, and CRC)
R/W Description
R Transmit End
TEND is set to 1 when the receiving end
acknowledges no error signal and the next transmit
data is ready to be transferred to TDR.
[Setting conditions]
•
When both TE and EPS in SCR are 0
•
When ERS = 0 and TDRE = 1 after a specified
time passed after the start of 1-byte data transfer.
The set timing depends on the register setting as
follows.
When GM = 0 and BLK = 0, 2.5 etu after transmission
start
When GM = 0 and BLK = 1, 1.5 etu after transmission
start
When GM = 1 and BLK = 0, 1.0 etu after transmission
start
When GM = 1 and BLK = 1, 1.0 etu after transmission
start
[Clearing conditions]
•
When 0 is written to TEND after reading TEND = 1
•
When a TXI interrupt request is issued allowing
DTC to write the next data to TDR
•
When BLK in SMR is 0 and RFU is activated by
TEND = 1 allowing data to be written to TDR (only
for SCI_0 and SCI_2)
•
When BLK in SMR is 1 and RFU is activated by
TDRE = 1 allowing data to be written to TDR (only
for SCI_0 and SCI_2)
R Multiprocessor Bit
Not used in smart card interface mode.
R/W Multiprocessor Bit Transfer
Write 0 to this bit in smart card interface mode.
Rev. 3.00 Jan 25, 2006 page 403 of 872
REJ09B0286-0300