Valid Strobes; Figure 6.4 Access Sizes And Data Alignment Control (16-Bit Access Space); Table 6.9 Data Buses Used And Valid Strobes - Renesas H8S/2158 User Manual

Section 6 Bus Controller
Byte size
Byte size
Word size
Longword
size

Figure 6.4 Access Sizes and Data Alignment Control (16-bit Access Space)

6.5.2

Valid Strobes

Table 6.9 shows the data buses used and valid strobes for each access space.
In a read, the RD signal is valid for both the upper and lower halves of the data bus. In a write, the
HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half.
Table 6.9 Data Buses Used and Valid Strobes
Access
Area Size
8-bit access Byte
space
16-bit access Byte
space
Word
Notes: Undefined
Invalid
Ports or others
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• Even address
• Odd address
1st bus cycle
2nd bus cycle
Read/
Write Address
Read —
Write —
Read Even
Odd
Write Even
Odd
Read —
Write —
: Undefined data is output.
: Input state with the input value ignored.
: Used as ports or I/O pins for on-chip peripheral modules, and are not
used as the data bus.
Upper data bus Lower data bus
D15 D8 D7
Valid Upper Data Bus
Strobe (D15 to D8)
RD
Valid
HWR
RD
Valid
Invalid
HWR
Valid
LWR
Undefined
RD
Valid
HWR, LWR
Valid
D0
Lower Data
Bus (D7 to D0)
Ports or others
Ports or others
Invalid
Valid
Undefined
Valid
Valid
Valid