Figure 5.5 Flowchart Of Procedure Up To Interrupt Acceptance In Interrupt Control - Renesas H8S/2158 User Manual

7. The CPU generates a vector address for the accepted interrupt and starts execution of the
interrupt handling routine at the address indicated by the contents of the vector address in the
vector table.
IRQ0
Figure 5.5 Flowchart of Procedure Up to Interrupt Acceptance
Program excution state
Interrupt generated?
Yes
An interrupt with interrupt
control level 1?
Yes
No
No
Yes
IRQ1
Yes
MMCIC
Yes
Save PC and CCR
Read vector address
Branch to interrupt handling routine
in Interrupt Control Mode 0
No
Yes
NMI
No
No
No
IRQ0
Yes
IRQ1
Yes
No
I = 0
Yes
I 1
Rev. 3.00 Jan 25, 2006 page 93 of 872
Section 5 Interrupt Controller
Hold pending
No
MMCIC
Yes
REJ09B0286-0300