Operation; Watchdog Timer Mode - Renesas H8S/2158 User Manual

Bit Bit Name Initial Value R/W
2 CKS2 0
1 CKS1 0
0 CKS0 0
Notes: 1. Only 0 can be written, to clear the flag.
2. When OVF is polled with the interval timer interrupt disabled, OVF = 1 must be read at
least twice.
15.4

Operation

15.4.1

Watchdog Timer Mode

To use the WDT as a watchdog timer, set the WT/IT bit and the TME bit in TCSR to 1. While the
WDT is used as a watchdog timer, if TCNT overflows without being rewritten because of a
system malfunction or another error, an internal reset or NMI interrupt request is generated. TCNT
does not overflow while the system is operating normally. Software must prevent TCNT
overflows by rewriting the TCNT value (normally be writing H'00) before overflows occurs.
Description
R/W Clock Select 2 to 0
R/W Selects the clock source to be input to TCNT. The
overflow cycle for φ = 25 MHz and φSUB = 32.768 kHz is
R/W
enclosed in parentheses.
When PSS = 0:
000: φ/2 (frequency: 20.4 µs)
001: φ/64 (frequency: 655.3 µs)
010: φ/128 (frequency: 1.3 ms)
011: φ/512 (frequency: 5.2 ms)
100: φ/2048 (frequency: 20.9 ms)
101: φ/8192 (frequency: 83.8 ms)
110: φ/32768 (frequency: 335.5 ms)
111: φ/131072 (frequency: 1.34 s)
When PSS = 1:
000: φSUB/2 (cycle: 15.6 ms)
001: φSUB/4 (cycle: 31.3 ms)
010: φSUB/8 (cycle: 62.5 ms)
011: φSUB/16 (cycle: 125 ms)
100: φSUB/32 (cycle: 250 ms)
101: φSUB/64 (cycle: 500 ms)
110: φSUB/128 (cycle: 1 s)
111: φ/256 (cycle: 2 s)
Section 15 Watchdog Timer (WDT)
Rev. 3.00 Jan 25, 2006 page 379 of 872
REJ09B0286-0300