Interrupts; Operation Timing; Figure 7.9 Dtc Operation Timing (Example In Normal Mode Or Repeat Mode) - Renesas H8S/2158 User Manual

7.5.5

Interrupts

An interrupt request is issued to the CPU when the DTC has completed the specified number of
data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt
activation, the interrupt set as the activation source is generated. These interrupts to the CPU are
subject to CPU mask level and priority level control by the interrupt controller.
In the case of software activation, a software-activated data transfer end interrupt (SWDTEND) is
generated.
When the DISEL bit is 1 and one data transfer has been completed, or the specified number of
transfers have been completed, after data transfer ends, the SWDTE bit is held at 1 and an
SWDTEND interrupt is generated. The interrupt handling routine will then clear the SWDTE bit
to 0.
When the DTC is activated by software, an SWDTEND interrupt is not generated during a data
transfer wait or during data transfer even if the SWDTE bit is set to 1.
7.5.6

Operation Timing

φ
DTC activation
request
DTC request
Address

Figure 7.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode)

Vector read
Transfer information
read
Section 7 Data Transfer Controller (DTC)
Data transfer
Read Write
Transfer information
write
Rev. 3.00 Jan 25, 2006 page 161 of 872
REJ09B0286-0300