Renesas H8S/2158 User Manual page 830

Section 27 Power-Down Modes
Before using this function to switch the clock, the PLL circuit must be started up to provide a
stable 24-MHz clock.
Bit Bit Name Initial Value
7 KWUL1 0
6 KWUL0 0
5 P6PUE 0
4, 3 — All 0
2 CKCHGE 0
1 — 0
0 PLCKS 0
Rev. 3.00 Jan 25, 2006 page 776 of 872
REJ09B0286-0300
R/W Description
R/W For details on bits 7 to 5, see section 9.6.4, System
Control Register 2 (SYSCR2).
R/W
R/W
R/(W) Reserved
The initial value should not be changed.
R/W Clock Change Enable
Specifies the next operating mode and system clock
source (φ or φ24) when the SLEEP instruction is
executed while the SSBY bit is set to 1 in high-speed
mode or medium-speed mode. If the SLEEP instruction
is executed while the SSBY bit is cleared to 0, the
system clock source is not switched and operation shifts
to sleep mode.
0: Enters software standby mode or watch mode, and
switches to the system clock source specified by the
PLCKS bit.
1: Directly switches to the system clock source specified
by the PLCKS bit.
R/(W) Reserved
The initial value should not be changed.
R/W PLL Clock Select
Specifies φ or φ24 as the system clock source in high-
speed mode or medium-speed mode. If the LSON bit in
LPWCR and this bit are both set to 1 simultaneously, the
subclock selection by the LSON bit has higher priority
than clock selection by this bit.
0: Specifies φ as the system clock source.
Executing the SLEEP instruction while PLCKS = 0 and
SSBY = 1 can switch the clock source to φ.
Executing the SLEEP instruction while LSON = 1 and
SSBY = 1 can switch the clock source to 32-kHz
φSUB.
1: Specifies φ24 as the system clock source.
Executing the SLEEP instruction while PLCKS = 1 and
SSBY = 1 can switch the clock source to φ24.