Figure 16.19 Sample Sci Transmission Operation In Clocked Synchronous Mode - Renesas H8S/2158 User Manual

2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmission. If the TIE bit in SCR is set to 1 at this time, a TXI interrupt request is generated.
Because the TXI interrupt routine writes the next transmit data to TDR before transmission of
the current transmit data has finished, continuous transmission can be enabled.
3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock
mode has been specified and synchronized with the input clock when use of an external clock
has been specified.
4. The SCI checks the TDRE flag at the timing for sending the last bit.
5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission
of the next frame is started.
6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TxD pin maintains the
output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request
is generated. The SCK pin is fixed high.
Figure 16.20 shows a sample flow chart for serial data transmission. Even if the TDRE flag is
cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1.
Make sure to clear the receive error flags to 0 before starting transmission. Note that clearing the
RE bit to 0 does not clear the receive error flags.
Synchronization
clock
Serial data
TDRE
TEND
TXI interrupt
request generated

Figure 16.19 Sample SCI Transmission Operation in Clocked Synchronous Mode

Section 16 Serial Communication Interface (SCI, IrDA, and CRC)
Transfer direction
Bit 0 Bit 1
Data written to TDR
and TDRE flag cleared
to 0 in TXI interrupt
service routine
1 frame
Bit 7 Bit 0 Bit 1
TXI interrupt
request generated
Rev. 3.00 Jan 25, 2006 page 439 of 872
Bit 6 Bit 7
TEI interrupt request
generated
REJ09B0286-0300