System Reset By Reso Signal; Counter Values During Transitions Between High-Speed, Sub-Active, And Watch Modes; Figure 15.8 Sample Circuit For Resetting The System By The Reso Signal - Renesas H8S/2158 User Manual

System Reset by RESO
15.6.5
Inputting the RESO output signal to the RESO pin of this LSI prevents the LSI from being
initialized correctly; the RESO signal must not be logically connected to the RES pin of the LSI.
To reset the entire system by the RESO signal, use the circuit as shown in figure 15.8.
Reset signal for entire system
Figure 15.8 Sample Circuit for Resetting the System by the RESO
15.6.6 Counter Values during Transitions between High-Speed, Sub-Active, and Watch
Modes
When WDT_1 is used as a clock counter and is allowed to transit between high-speed mode and
sub-active or watch mode, the counter does not display the correct value due to internal clock
switching.
Specifically, when transiting from high-speed mode to sub-active or watch mode, that is, when the
control clock for WDT_1 switches from the main clock to the sub-clock, the counter incrementing
timing is delayed for approximately two to three clock cycles.
Similarly, when transiting from sub-active or watch mode to high-speed mode, the clock is not
supplied until stabilized internal oscillation is available because the main clock pulse generator is
halted in sub-clock mode. The counter is therefore prevented from incrementing for the time
specified by the STS2 to STS0 bits in SBYCR after internal oscillation starts, thus producing
counter value differences for this time.
Special care must be taken when using WDT_1 as a clock counter. Note that no counter value
difference is produced while operated in the same mode.
RESO Signal
RESO RESO
Reset input
Section 15 Watchdog Timer (WDT)
This LSI
RES
RESO
RESO Signal
RESO RESO
Rev. 3.00 Jan 25, 2006 page 385 of 872
REJ09B0286-0300