Table 17.8 Examples Of Operation Using Dtc - Renesas H8S/2158 User Manual

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Section 17 I C Bus Interface (IIC)

Table 17.8 Examples of Operation Using DTC

Master Transmit
Item Mode
Slave address + Transmission by
R/W bit DTC (ICDR write)
transmission/
reception
Dummy data —
read
Actual data Transmission by
transmission/ DTC (ICDR write)
reception
Dummy data —
(H'FF) write
Last frame Not necessary
processing
Transfer 1st time: Clearing
request by CPU
processing after
2nd time: End
last frame
condition issuance
processing
by CPU
Setting of Transmission:
number of DTC Actual data count
transfer data + 1 (+1 equivalent
frames to slave address +
R/W bits)
Rev. 3.00 Jan 25, 2006 page 532 of 872
REJ09B0286-0300
Master Receive Slave Transmit
Mode Mode
Transmission by Reception by
CPU (ICDR write) CPU (ICDR read)
Processing by —
CPU (ICDR read)
Reception by Transmission by
DTC (ICDR read) DTC (ICDR write)
— Processing by
DTC (ICDR write)
Reception by Not necessary
CPU (ICDR read)
Not necessary Automatic clearing
on detection of
end condition
during
transmission of
dummy data
(H'FF)
Reception: Actual Transmission:
data count Actual data count
+ 1 (+1 equivalent
to dummy data
(H'FF))
Slave Receive
Mode
Reception by CPU
(ICDR read)
—
Reception by DTC
(ICDR read)
—
Reception by CPU
(ICDR read)
Not necessary
Reception: Actual
data count