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13.3.4 Time Control
Register (TCR)
Table 13.2 Clock
Input to TCNT and
Count Condition
—
13.7 Input Capture
Operation
13.9.6 Mode Setting
with Cascaded
Connection
15.3 Register
Descriptions
16.3.7 Serial Status
Register (SSR)
Rev. 3.00 Jan 25, 2006 page x of lii
Page
Revision (See Manual for Details)
322
Table 13.2 amended
TMR_Y when (CKS2, CKS1, CKS0) = (1, 0, 0) (Before)
Increments at overflow signal from TCNT_X * → (After) Setting
prohibited
TMR_X when (CKS2, CKS1, CKS0) = (1, 0, 0) (Before)
Increments at compare-match A from TCNT_Y → (After)
Setting prohibited
Note * amended
Note: * If the TMR_0 clock input is ... , a count-up clock cannot
be generated. Simultaneous setting of this condition should
therefore be avoided.
—
Description of "TMR_Y and TMR_X Cascaded Connection"
deleted
336
Section number amended
344
Description amended
If the 16-bit count mode ... , the input clock pulses for TCNT_0
and TCNT_1 are not generated,
378
• TCSR_1
Notes amended
R/(W) *
1
[Setting conditions] ...
• When TCSR is read when OVF = 1 *
OVF ...
402
Description amended
Bit Functions in Smart card Interface Mode (when SMIF in
SCMR = 1)
Bit 6 [Clearing conditions] ...
• When RFU is activated by RDRF = 1 allowing data to be read
from RDR (only for SCI_0 and SCI_2)
2
, then 0 is written to
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