Rfu Initialization; Figure 8.13 Rfu Initialization Flow - Renesas H8S/2158 User Manual

8.10

RFU Initialization

Figure 8.13 shows the initialization flow of the RFU.
Clear DTSTRA, DTSTRB, DTSTRC
Set DTCRA (Sz, BUD(2-0), PMD1, PMD0)
Set DTIDR, DTIDSRA, DTIDSRSB
1. The initial state of the FIFO is the FIFO empty state. When a single data block is transferred
from RAM to the peripheral module, first initialize the RFU and then clear the FIFO empty
state by writing 1 to the STCLR bit in DTCRB.
2. If the DTE bit is cleared to 0, the FIFO full state is automatically canceled and then the FIFO
empty state is entered.
3. In medium-speed mode, the DTSPEED bit in SBYCR should be set to 1.
Clear DTE bit in DTCRD
Clear RAR, WAR, TMP
Set BAR
Set DTCRB
Set DTIER
Set DTCRA (IDE-A, IDE-B)
Set DTE bit in DTCRD

Figure 8.13 RFU Initialization Flow

Section 8 RAM-FIFO Unit (RFU)
Disable the relevant pointer set
Clear the pointer
Clear each setting
Set the base address
Transfer word/byte data and
set the boundary size and pointer mode
Enable use of status flags
Assign an ID and set the transfer direction
Set the interrupt enable bits
Enable the ID
Set the pointer set enable bit
Rev. 3.00 Jan 25, 2006 page 203 of 872
REJ09B0286-0300