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5.2
Input/Output Pins
Table 5.1 summarizes the pins of the interrupt controller.
Table 5.1
Pin Configuration
Symbol
NMI
IRQ15 to IRQ0
ExIRQ15 to ExIRQ2
KIN9 to KIN0
WUE15 to WUE8
5.3
Register Descriptions
The interrupt controller has the following registers. For details on the system control register
(SYSCR), see section 3.2.2, System Control Register (SYSCR), and for details on the IRQ sense
port select registers (ISSR16, ISSR), see section 9.11.1, IRQ Sense Port Select Register 16
(ISSR16), IRQ Sense Port Select Register (ISSR).
• Interrupt control registers A to D (ICRA to ICRD)
• Address break control register (ABRKCR)
• Break address registers A to C (BARA to BARC)
• IRQ sense control registers (ISCR16H, ISCR16L, ISCRH, ISCRL)
• IRQ enable registers (IER16, IER)
• IRQ status registers (ISR16, ISR)
• Keyboard matrix interrupt mask registers (KMIMRA, KMIMR6)
• Wake-up event interrupt mask registers (WUEMR3)
I/O
Function
Input
Nonmaskable external interrupt
Rising edge or falling edge can be selected
Input
Maskable external interrupts
Rising edge, falling edge, or both edges, or level sensing, can
be selected individually for each pin. Pin of IRQn or ExIRQn to
input IRQ15 to IRQ2 interrupts can be selected.
Input
Maskable external interrupts
An interrupt is requested at falling edge.
Input
Maskable external interrupts
An interrupt is requested at falling edge.
Section 5 Interrupt Controller
Rev. 3.00 Jan 25, 2006 page 75 of 872
REJ09B0286-0300
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