Renesas H8S/2158 User Manual page 41

Figure 14.6 2fH Modification Timing Chart............................................................................ 364
Figure 14.7 Fall Modification and IHI Synchronization Timing Chart.................................... 366
Figure 14.8 IVG Signal/IHG Signal/CL4 Signal Timing Chart............................................... 369
Figure 14.9 CBLANK Output Waveform Generation ............................................................. 372
Section 15 Watchdog Timer (WDT)
Figure 15.1 Block Diagram of WDT ....................................................................................... 374
Figure 15.2 Watchdog Timer Mode (RST/NMI = 1) Operation .............................................. 380
Figure 15.3 Interval Timer Mode Operation ............................................................................ 381
Figure 15.4 OVF Flag Set Timing ........................................................................................... 381
Output Timing of RESO Signal............................................................................ 382
Figure 15.5
Figure 15.6 Writing to TCNT and TCSR (WDT_0) ................................................................ 383
Figure 15.7 Conflict between TCNT Write and Increment...................................................... 384
Sample Circuit for Resetting the System by the RESO Signal ............................. 385
Figure 15.8
Section 16 Serial Communication Interface (SCI, IrDA, and CRC)
Figure 16.1 Block Diagram of SCI_1 ...................................................................................... 389
Figure 16.2 Block Diagram of SCI_0 and SCI_2 .................................................................... 390
Figure 16.3 Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits) ............................................... 417
Figure 16.4 Receive Data Sampling Timing in Asynchronous Mode...................................... 419
Figure 16.5 Relation between Output Clock and Transmit Data Phase
(Asynchronous Mode) .......................................................................................... 420
Figure 16.6 Basic Clock Examples When Average Transfer Rate Is Selected (1)................... 422
Figure 16.7 Basic Clock Examples When Average Transfer Rate Is Selected (2)................... 423
Figure 16.8 Sample SCI Initialization Flowchart..................................................................... 424
Figure 16.9 Example of Operation in Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit) ................................................. 425
Figure 16.10 Sample Serial Transmission Flowchart................................................................. 426
Figure 16.11 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity,
One Stop Bit) ........................................................................................................ 427
Figure 16.12 Sample Serial Reception Flowchart (1) ................................................................ 429
Figure 16.12 Sample Serial Reception Flowchart (2) ................................................................ 430
Figure 16.13 Example of Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A).......................................... 432
Figure 16.14 Sample Multiprocessor Serial Transmission Flowchart........................................ 433
Figure 16.15 Example of SCI Operation in Reception (Example with 8-Bit Data,
Multiprocessor Bit, One Stop Bit) ........................................................................ 434
Figure 16.16 Sample Multiprocessor Serial Reception Flowchart (1) ....................................... 435
Figure 16.16 Sample Multiprocessor Serial Reception Flowchart (2) ....................................... 436
Figure 16.17 Data Format in Synchronous Communication (LSB-First) .................................. 437
Rev. 3.00 Jan 25, 2006 page xxxix of lii