Renesas H8S/2158 User Manual page 404

Section 14 Timer Connection
Bit Bit Name
3 HFINV
2 VFINV
1 HIINV
0 VIINV
Rev. 3.00 Jan 25, 2006 page 350 of 872
REJ09B0286-0300
Initial Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
Description
Input Synchronization Signal Inversion
These bits select inversion of the input phase of the
spare horizontal synchronization signal (HFBACKI),
the spare vertical synchronization signal (VFBACKI),
the horizontal synchronization signal (HSYNCI),
composite synchronization signal (CSYNCI), and the
vertical synchronization signal (VSYNCI).
•
HFINV
0: The HFBACKI pin state is used directly as the
HFBACKI input
1: The HFBACKI pin state is inverted before use
as the HFBACKI input
•
VFINV
0: The VFBACKI pin state is used directly as the
VFBACKI input
1: The VFBACKI pin state is inverted before use
as the VFBACKI input
•
HIINV
0: The HSYNCI and CSYNCI pin states are used
directly as the HSYNCI and CSYNCI inputs
1: The HSYNCI and CSYNCI pin states are
inverted before use as the HSYNCI and
CSYNCI inputs
•
VIINV
0: The VSYNCI pin state is used directly as the
VSYNCI input
1: The VSYNCI pin state is inverted before use
as the VSYNCI input