Table of Contents
Advertisement
Item
17.3.8 IIC Operation
Reservation Adapter
Status Register A
(ICSRA)
17.3.10 IIC
Operation Reservation
Adapter Status
Register C (ICSRC)
Figure 17.3 State
Transitions of TDRE,
SDRF, and RDRF Bits
17.5.3 Master
Receive Operation
17.7 Usage Notes
Table 17.12
Permissible SCL Rise
Time (t
) Values
sr
Rev. 3.00 Jan 25, 2006 page xii of lii
Page
Revision (See Manual for Details)
498
Bit table amended
ACKXE
(Before) R/W → (After) R
506
Description amended
Bit 0 [Clearing conditions]
• When ICDRX is read from with no receive data in the shift
register (SDRF = 0) in receive mode ...
507
Figure 17.3 amended
(b) Receive mode
(Before) TDRE → (After) SDRE
(Before) SDRF → (After) RDRF
520
Description amended
9. Clear the IRIC flag in ICCR to cancel wait state.
The master device outputs the 9th clock and drives SDA low at
9th receive clock pulse ...
542
Table 17.12 amended
IICX1,
t
cyc
IICX0
Indication
1
17.5 t
cyc
2
I
C Bus
φ =
Specification
(Max.)
5 MHz
Standard mode
1000
1000
Time Indication[ns]
φ =
φ =
φ =
φ =
8 MHz
10 MHz
16 MHz
20 MHz
1000
1000
1000
875
φ =
25 MHz
700
Advertisement
Table of Contents
