Table 14.6 Examples Of Tcr And Tcsr Settings - Renesas H8S/2158 User Manual

Section 14 Timer Connection

Table 14.6 Examples of TCR and TCSR Settings

Register Bit
TCR in TMR_1 7
6
5
4, 3
2 to 0
TCSR in TMR_1 3 to 0
TCR in FRT 6
1, 0
TCSR in FRT 0
Rev. 3.00 Jan 25, 2006 page 362 of 872
REJ09B0286-0300
Abbreviation Contents
CMIEB 0
CMIEA 0
OVIE 0
CCLR1, CCLR0 11
CKS2 to CKS0 101
OS3 to OS0 0011
1001
IEDGB 0/1
CKS1, CKS0 01
CCLRA 0
Description
Interrupts due to compare-match and
overflow are disabled
TCNT is cleared by the rising edge of
the external reset signal (inverse of
the IVI signal)
TCNT is incremented on the rising
edge of the external clock (IHI signal)
Not changed by compare-match B;
output inverted by compare-match A
(toggle output): Division by 512
When TCORB < TCORA, 1 output
on compare-match B, and 0 output
on compare-match A: Division by
256
0: FRC value is transferred to ICRB
on falling edge of input capture
input B (IHI divided signal
waveform)
1: FRC value is transferred to ICRB
on rising edge of input capture
input B (IHI divided signal
waveform)
FRC is incremented on internal
clock: φ/8
FRC clearing is disabled