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2. CPU
2.6.2
Access to On-Chip Peripheral Modules
On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits,
so access is by byte size only. This means that for accessing word data, two instructions must be
used. Figures 2.12 and 2.13 show the on-chip peripheral module access cycle.
Two-State Access to On-Chip Peripheral Modules
φ or φ
SUB
Internal address bus
Internal read signal
Internal data bus
(read access)
Internal write signal
Internal data bus
(write access)
Figure 2.12 On-Chip Peripheral Module Access Cycle (2-State Access)
Rev.3.00 Jul. 19, 2007 page 56 of 532
REJ09B0397-0300
Bus cycle
T
state
1
Address
Read data
Write data
T
state
2
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