Renesas H8S/2158 User Manual page 39

Figure 7.10 DTC Operation Timing (Example of Block Transfer Mode,
with Block Size of 2) ............................................................................................ 162
Figure 7.11 DTC Operation Timing (Example of Chain Transfer).......................................... 162
Section 8 RAM-FIFO Unit (RFU)
Figure 8.1 Block Diagram of RFU......................................................................................... 168
Figure 8.2 Examples of Temporary Cancellation of Medium-Speed Mode .......................... 188
Figure 8.3 Example of RFU Response Time ........................................................................ 190
Figure 8.4 RFU Interface of USB .......................................................................................... 194
Figure 8.5 Operation Flow of USB IN Transfer .................................................................... 195
Figure 8.6 Operation Flow of USB OUT Transfer................................................................. 196
Figure 8.7 RFU Interface of SCI............................................................................................ 197
Figure 8.8 Operation Flow of SCI Transmission ................................................................... 198
Figure 8.9 Operation Flow of SCI Reception......................................................................... 199
Figure 8.10 RFU Interface of MCIF ........................................................................................ 200
Figure 8.11 Operation Flow of MCIF Transmission................................................................ 201
Figure 8.12 Operation Flow of MCIF Reception ..................................................................... 202
Figure 8.13 RFU Initialization Flow ........................................................................................ 203
Section 10 8-Bit PWM Timer (PWM)
Figure 10.1 Block Diagram of PWM Timer ............................................................................ 262
Figure 10.2 Example of Additional Pulse Timing
(When Upper 4 Bits of PWDR = B'1000) ............................................................ 271
Section 11 14-Bit PWM Timer (PWMX)
Figure 11.1 PWM (D/A) Block Diagram................................................................................. 273
Figure 11.2 PWM (D/A) Operation ......................................................................................... 281
Figure 11.3 Output Waveform (OS = 0, DADR corresponds to T
Figure 11.4 Output Waveform (OS = 1, DADR corresponds to T
Figure 11.5 D/A Data Register Configuration when CFS = 1 ................................................. 284
Figure 11.6 Output Waveform when DADR = H'0207 (OS = 1)............................................. 285
Section 12 16-Bit Free-Running Timer (FRT)
Figure 12.1 Block Diagram of 16-Bit Free-Running Timer..................................................... 288
Figure 12.2 Example of Pulse Output ...................................................................................... 299
Figure 12.3 Increment Timing with Internal Clock Source...................................................... 300
Figure 12.4 Increment Timing with External Clock Source .................................................... 300
Figure 12.5 Timing of Output Compare A Output................................................................... 301
Figure 12.6 Clearing of FRC by Compare-Match A Signal..................................................... 301
Figure 12.7 Input Capture Input Signal Timing (Usual Case) ................................................. 302
Figure 12.8 Input Capture Input Signal Timing (When ICRA to ICRD Is Read).................... 302
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Rev. 3.00 Jan 25, 2006 page xxxvii of lii