Register Descriptions; Figure 7.1 Block Diagram Of Dtc - Renesas H8S/2158 User Manual

Section 7 Data Transfer Controller (DTC)
Interrupt controller
Interrupt
request
CPU interrupt
request
Legend:
MRA, MRB
CRA, CRB
SAR
DAR
DTCERA to DTCERE
DTVECR
7.2

Register Descriptions

The DTC has the following registers.
• DTC mode register A (MRA)
• DTC mode register B (MRB)
• DTC source address register (SAR)
• DTC destination address register (DAR)
• DTC transfer count register A (CRA)
• DTC transfer count register B (CRB)
These six registers cannot be directly accessed from the CPU. When a DTC activation interrupt
source occurs, the DTC reads a set of register information that is stored in on-chip RAM to the
corresponding DTC registers and transfers data. After the data transfer, it writes a set of updated
register information back to on-chip RAM.
Rev. 3.00 Jan 25, 2006 page 146 of 872
REJ09B0286-0300
DTC
: DTC mode register A, B
: DTC transfer count register A, B
: DTC source address register
: DTC destination register
: DTC enable registers A to E
: DTC vector register

Figure 7.1 Block Diagram of DTC

Internal address bus
Internal data bus
On-chip RAM