Renesas H8S/2158 User Manual page 552

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Section 17 I C Bus Interface (IIC)
Bit Bit Name Initial Value
3 MSTX 0
2 TRSX 0
1 WAITX 0
0 ACKXE 0
Rev. 3.00 Jan 25, 2006 page 498 of 872
REJ09B0286-0300
R/W Description
R Master/Slave State X
R Transmit/Receive State X
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
These bits are automatically set by an operation
reservation command.
R Wait Insertion Bit X
This bit is valid only in master mode with the I
format. This bit is automatically set by an operation
reservation command.
0: Data and the acknowledge bit are transferred
consecutively with no wait inserted.
1: After the fall of the clock for the final data bit, a wait
state begins (with SCL at the low level).
R Acknowledge Bit Decision Selection X
0: The value of the acknowledge bit is ignored, and
continuous transfer is performed. The value of the
received acknowledge bit is not indicated by the
ACKBX bit in ICCRX, which is always 0.
1: If the acknowledge bit is 1, continuous transfer is
halted.
This bit is automatically set by an operation reservation
command.
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C bus