Renesas H8S/2158 User Manual page 541

Bit Bit Name Initial Value R/W
3 ACKE 0
2 BBSY 0
0 SCP 1
Description
R/W Acknowledge Bit Decision Selection
0: The value of the received acknowledge bit is ignored,
and continuous transfer is performed. The value of the
received acknowledge bit is not indicated by the ACKB
bit in ICSR, which is always 0.
1: If the received acknowledge bit is 1, continuous
transfer is halted.
Depending on the receiving device, the acknowledge bit
may be significant, in indicating completion of processing
of the received data, for instance, or may be fixed at 1
and have no significance.
R/W Bus Busy
W Start Condition/Stop Condition Prohibit
In master mode:
Writing 0 in BBSY and 0 in SCP: A stop condition is
issued
Writing 1 in BBSY and 0 in SCP: A start condition and a
restart condition are issued
In slave mode:
Writing to the BBSY flag is disabled.
[BBSY setting condition]
•
When the SDA level changes from high to low under
the condition of SCL = high, assuming that the start
condition has been issued.
[BBSY clearing condition]
•
When the SDA level changes from low to high under
the condition of SCL = high, assuming that the start
condition has been issued.
To issue a start/stop condition, use the MOV instruction.
2
The I C bus interface must be set in master transmit
mode before the issue of a start condition. Set MST to 1
and TRS to 1 before writing 1 in BBSY and 0 in SCP.
The BBSY flag can be read to check whether the I
(SCL, SDA) is busy or free.
The SCP bit is always read as 1. If 0 is written, the data is
not stored.
2
Section 17 I C Bus Interface (IIC)
Rev. 3.00 Jan 25, 2006 page 487 of 872
2
C bus
REJ09B0286-0300