Renesas H8S/2158 User Manual page 16

Item
17.7 Usage Notes
Rev. 3.00 Jan 25, 2006 page xiv of lii
Page Revision (See Manual for Details)
550, 16. Notes on Arbitration Lost
551
2
The I C bus interface recognizes the data in transmit/receive
frame as an address when arbitration is lost in master mode
and a transition to slave receive mode is automatically carried
out.
When arbitration is lost not in the first frame but in the second
frame or subsequent frame, transmit/receive data that is not an
address is compared with the value set in the SAR or SARX
register as an address. If the receive data matches with the
address in the SAR or SARX register, the I
erroneously recognizes that the address call has occurred. (See
figure 17.29.)
In multi-master mode, a bus conflict could happen. When The
2
I C bus interface is operated in master mode, check the state of
the AL bit in the ICSR register every time after one frame of
data has been transmitted or received.
When arbitration is lost during transmitting the second frame or
subsequent frame, take avoidance measures.
2
I C bus interface
(Master transmit mode)
Other device
(Master transmit mode)
2
I C bus interface
(Slave receive mode)
Figure 17.29 Diagram of Erroneous Operation when
Arbitration is Lost
Though it is prohibited in the normal I
problem may occur when the MST bit is erroneously set to 1
and a transition to master mode is occurred during data
transmission or reception in slave mode. In multi-master mode,
pay attention to the setting of the MST bit when a bus conflict
may occur. In this case, the MST bit in the ICCR register should
be set to 1 according to the order below.
(a) Make sure that the BBSY flag in the ICCR register is 0 and
the bus is free before setting the MST bit.
• Arbitration is lost
• The AL flag in ICSR is set to 1
S SLA A
R/W
Transmit data match
Transmit timing match
A
S SLA R/W
A
S SLA R/W SLA
• Receive address is ignored • Automatically transferred to slave
receive mode
• Receive data is recognized as
an address
• When the receive data matches to
the address set in the SAR or SARX
register, the I
as a slave device
2
C bus interface
DATA1
Transmit data does not match
DATA2 A DATA3
Data contention
R/W A DATA4
2
C bus interface operates
2
C protocol, the same
A
A