Hardware Standby Mode; Figure 27.3 Software Standby Mode Application Example - Renesas H8S/2158 User Manual

Section 27 Power-Down Modes
Oscillator
φ
NMI
NMIEG
SSBY
NMI exception
handling
NMIEG = 1
SSBY = 1

Figure 27.3 Software Standby Mode Application Example

27.6

Hardware Standby Mode

The CPU makes a transition to hardware standby mode from any mode when the STBY pin is
driven low.
In hardware standby mode, all functions enter the reset state. As long as the prescribed voltage is
supplied, on-chip RAM data is retained. The I/O ports are set to the high-impedance state.
In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before
driving the STBY pin low. Do not change the state of the mode pins (MD2, MD1, and MD0)
while this LSI is in hardware standby mode.
Hardware standby mode is cleared by the STBY pin input or the RES pin input.
When the STBY pin is driven high while the RES pin is low, clock oscillation is started. Ensure
that the RES pin is held low until system clock oscillation stabilizes. When the RES pin is
subsequently driven high after the clock oscillation stabilization time has passed, reset exception
handling starts.
Rev. 3.00 Jan 25, 2006 page 784 of 872
REJ09B0286-0300
Software standby mode
(power-down mode)
SLEEP instruction
NMI exception
Oscillation
handling
stabilization
time t
OSC2