Figure 16.37 Irda Transmission And Reception - Renesas H8S/2158 User Manual

The high-level pulse width is defined to be 1.41 µs at minimum and (3/16 + 2.5%) × bit rate or
(3/16 × bit rate) +1.08 µs at maximum. For example, when the frequency of system clock φ is 20
MHz, a high-level pulse width of at least 1.4 µs to 1.6 µs can be specified.
For serial data of level 1, no pulses are output.
Reception: During reception, IR frames are converted to UART frames using the IrDA interface
before inputting to SCI_1.
Data of level 0 is output each time a high-level pulse is detected and data of level 1 is output when
no pulse is detected in a bit cycle. If a pulse has a high-level width of less than 1.41 µs, the
minimum width allowed, the pulse is recognized as level 0.
High-Level Pulse Width Selection: Table 16.12 shows possible settings for bits IrCKS2 to
IrCKS0 (minimum pulse width), and this LSI's operating frequencies and bit rates, for making the
pulse width shorter than 3/16 times the bit rate in transmission.
Section 16 Serial Communication Interface (SCI, IrDA, and CRC)
UART frame
Start
bit
0 1 0 1
Transmission
IR frame
Start
bit
0 1 0 1
Bit
cycle

Figure 16.37 IrDA Transmission and Reception

Data
0 0 1 1
Reception
Data
0 0 1 1
Pulse width is 1.6 µs to
3/16 bit cycle
Rev. 3.00 Jan 25, 2006 page 457 of 872
Stop
bit
0 1
Stop
bit
0 1
REJ09B0286-0300