Operation; Pwm Decoding (Pdc Signal Generation); Table 14.4 Examples Of Tcr Settings; Table 14.5 Examples Of Tcorb (Pulse Width Threshold) Settings - Renesas H8S/2158 User Manual

Section 14 Timer Connection
14.4

Operation

14.4.1

PWM Decoding (PDC Signal Generation)

The timer connection facility and TMR_X can be used to decode a PWM signal in which 0 and 1
are represented by the pulse width. To do this, a signal in which a rising edge is generated at
regular intervals must be selected as the IHI signal.
The timer counter (TCNT) in TMR_X is set to count the internal clock pulses and to be cleared on
the rising edge of the external reset signal (IHI signal). The value to be used as the threshold for
deciding the pulse width is written in TCORB. The PWM decoder contains a delay latch which
uses the IHI signal as data and compare-match signal B (CMB) as a clock, and the state of the IHI
signal (the result of the pulse width decision) at the first compare-match signal B timing after
TCNT is reset by the rise of the IHI signal is output as the PDC signal.
The pulse width setting using TICRR and TICRF of TMR_X can be used to determine the pulse
width decision threshold. Examples of TCR and TCORB settings of TMR_X are shown in tables
14.4 and 14.5, and the PWM decoding timing chart is shown in figure 14.2.

Table 14.4 Examples of TCR Settings

Bit Abbreviation
7 CMIEB
6 CMIEA
5 OVIE
4, 3 CCLR1, CCLR0
2 to 0 CKS2 to CKS0

Table 14.5 Examples of TCORB (Pulse Width Threshold) Settings

φ φ φ φ : 10 MHz
H'07 0.8 µs
H'0F 1.6 µs
H'1F 3.2 µs
H'3F 6.4 µs
H'7F 12.8 µs
Rev. 3.00 Jan 25, 2006 page 358 of 872
REJ09B0286-0300
Contents Description
0 Interrupts due to compare-match and overflow are
disabled
0
0
11 TCNT is cleared by the rising edge of the external
reset signal (IHI signal)
001 Incremented on internal clock (φ)
φ φ φ φ : 12 MHz
0.67 µs
1.33 µs
2.67 µs
5.33 µs
10.67 µs
φ φ φ φ : 16 MHz φ φ φ φ : 20 MHz
0.5 µs 0.4 µs
1.0 µs 0.8 µs
2.0 µs 1.6 µs
4.0 µs 3.2 µs
8.0 µs 6.4 µs