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SDA
SCL
1–7
S
SLA
Legend:
S:
Start condition. The master device drives SDA from high to low while SCL is high.
SLA:
Slave address
R/W:
Indicates the direction of data transfer: From the slave device to the master device when
R/W is 1, or from the master device to the slave device when R/W is 0.
A:
Acknowledge signal. The receiving device drives SDA to low.
DATA: Transmit/Receive data
P:
Stop condition. The master device drives SDA from low to high while SCL is high.
17.5.2
Master Transmit Operation
When data is set to ICDR during the period between the execution of an instruction to issue a start
condition and the creation of the start condition, the data may not be output normally, because
there will be a conflict between generation of a start condition and output of data. Although data
H'FF is to be sent to ICDR by a dummy write operation before an issue of a stop condition, the
H'FF data may be output by the dummy write operation if the execution of the instruction to issue
a stop condition is delayed. To prevent these problems, follow the flowchart shown below during
the master transmit operation.
2
In I
C bus format master transmit mode, the master device outputs the transmit clock and transmit
data, and the slave device returns an acknowledge signal. The transmission procedure and
operations for sequential data transmission in synchronization with the ICDR writing are described
below.
1. Set the ICE bit in ICCR to 1. Set bits MLS, WAIT, and CKS2 to CKS0 in ICMR, and bits
IICX1 and IICX0 in STCR, according to the operating mode.
2. Read the BBSY flag in ICCR to confirm that the bus is free.
3. Set bits MST and TRS to 1 in ICCR to select master transmit mode.
4. Write 1 to BBSY and 0 to SCP in ICCR. This changes SDA from high to low when SCL is
high, and generates the start condition.
8
9
1–7
R/W
A
DATA
Figure 17.6 I
Section 17 I
8
9
1–7
A
2
C Bus Timing
Rev. 3.00 Jan 25, 2006 page 517 of 872
2
C Bus Interface (IIC)
8
9
DATA
A/A
REJ09B0286-0300
P
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