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This LSI has an on-chip bus controller (BSC) that manages the bus width and the number of
access states of the external address space. The BSC also has a bus arbitration function, and
controls the operation of the internal bus masters—CPU, data transfer controller (DTC), and RAM
FIFO unit (RFU).
6.1
Features
• Expansion area division
The external address space can be accessed as basic expansion areas
A 256-kbyte expansion area can be set and controlled independently of basic expansion
areas in mode 2 (advanced mode)
A CP expansion area can be set and controlled independently of basic expansion areas in
mode 2 (advanced mode)
• Address pin reduction
A 256-kbyte expansion area from H'F80000 to H'FBFFFF can be selected using 18 address
pins and the CS256 signal
A CP expansion area (8 kbytes, basic mode) from H'FFC000 to H'FFDFFF can be selected
using 13 address pins and the CPCS1 signal
A 2-kbyte area from H'(FF)F000 to H'(FF)F7FF can be selected using six to eleven address
pins and the IOS signal
• Basic bus interface
2-state access or 3-state access can be selected for each area
Program wait states can be inserted for each area
• Memory card interface
A CompactFlash * interface can be supported for the CF expansion area (4 kbytes, memory
card mode) in the CP expansion area
• Burst ROM interface
A burst ROM interface can be set for basic expansion areas
1-state access or 2-state access can be selected for burst access
• Idle cycle insertion
An idle cycle can be inserted for external write cycles immediately after external read
cycles
• Bus arbitration function
Includes a bus arbiter that arbitrates bus mastership between the CPU, DTC, and RFU
BSCS200A_000020020300
Section 6 Bus Controller
Section 6 Bus Controller
Rev. 3.00 Jan 25, 2006 page 103 of 872
REJ09B0286-0300
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