Transfer Clock Control Register (Clkon) - Renesas H8S/2158 User Manual

Section 19 Multimedia Card Interface (MCIF)
Bit Bit Name
0 MMCPE

19.3.16 Transfer Clock Control Register (CLKON)

CLKON controls the transfer clock frequency and clock ON/OFF.
A 20-MHz system clock is needed, and bits CSEL2 to CSEL0 should be set to B'100 for a 20-
Mbps transfer clock according to the limitation of the maximum operating frequency of this LSI.
At this time, bits CSEL2 to CSEL0 should be cleared to B'000 for a 200-kbps transfer clock in the
open drain format output status in MMC mode.
Bit Bit Name
7 CLKON
6 —
to
3
2 CSEL2
1 CSEL1
0 CSEL0
Rev. 3.00 Jan 25, 2006 page 654 of 872
REJ09B0286-0300
Initial Value R/W
0 R/W
Initial Value R/W
0 R/W
All 0 R
0 R/W
0 R/W
0 R/W
Description
MCIF Pin Function Enable
Enables/disables input/output of all MCIF
input/output pins.
0: Disables all inputs/outputs.
1: Enables MCCLK, MCCMD/MCTxD,
MCDAT/MCRxD, MCCSA/MCDATDIR, and
MCCSB/MCCMDDIR pin inputs/outputs.
Outputs of the MCCSB and MCDATDIR and
MCCMDDIR pins are also disabled via the
SPCNUM bit and DIRME bit, respectively.
Description
Clock On
0: Fixes the transfer clock output from the
MCCLK pin to low.
1: Outputs the transfer clock from the MCCLK
pin.
Reserved
These bits are always read as 0 and cannot be
modified.
Transfer Clock Frequency Select
000: Uses φ/100 as a transfer clock.
001: Uses φ/8 as a transfer clock.
010: Uses φ/4 as a transfer clock.
011: Uses φ/2 as a transfer clock.
100: Uses φ as a transfer clock.
101 to 111: Setting prohibited