Port 5; Port 5 Data Direction Register (P5Ddr) - Renesas H8S/2158 User Manual

Section 9 I/O Ports
MCIF MCIF disable (MMCPE in IOMCR is 0)
operating
mode
P40DDR
Pin function P40 input pin
9.5

Port 5

Port 5 is an 8-bit I/O port. Port 5 pins also function as interrupt input pins, the PWMX output pin,
SCI_0, SCI_1, and SCI_2 input/output pins. Port 5 has the following registers.

• Port 5 data direction register (P5DDR)

• Port 5 data register (P5DR)
9.5.1 Port 5 Data Direction Register (P5DDR)
The individual bits of P5DDR specify input or output for the pins of port 5.
Bit Bit Name
7 P57DDR
6 P56DDR
5 P55DDR
4 P54DDR
3 P53DDR
2 P52DDR
1 P51DDR
0 P50DDR
Rev. 3.00 Jan 25, 2006 page 228 of 872
REJ09B0286-0300
or
(Single-chip mode (EXPE = 0)
MMCS in PTCNT0 is 0)
0
P40 output pin
TMI0 (TMCI0/TMRI0) input pin/IRQ0 input pin
Initial Value R/W
0 W
0 W
0 W
0 W
0 W
0 W
0 W
0 W
MCIF enable (MMCPE in IOMCR is 1)
MMCS in PTCNT0 is 1
Extended mode (EXPE = 1)
1
ExMCCLK output pin
Description
If port 5 pins are specified for use as the general
I/O port, the corresponding port 5 pins are output
ports when the P5DDR bits are set to 1, and input
ports when cleared to 0.
or
—