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Section 11 14-Bit PWM Timer (PWMX)
Table 11.3 Settings and Operation (Examples when φ φ φ φ = 25 MHz)
PCSR
Resolution
CKS
PWCKXB PWCKXA
0
0
0
1
0
1
1
1
0
1
Note: * Indicates the conversion cycle when specific DADR bits are fixed.
Rev. 3.00 Jan 25, 2006 page 282 of 872
REJ09B0286-0300
Base Cycle
Conversion
CFS
(µs)/
Cycle (µs)/
T (µs)
Frequency
Frequency
0.04
0
2.56/
391 kHz
1
10.24/
97.7 kHz
0.08
0
5.12/
195 kHz
1
20.48/
48.8 kHz
2.56
0
163.84/
6.10 kHz
1
655.36/
1.53 kHz
5.12
0
327.68/
3.05 kHz
1
1310.72/
763 Hz
TL/TH
(OS = 0/OS = 1)
655.36/
1. Always low/high
1.53 kHz
output (DADR =
H'0001 to H'03FD)
2. (Data value) × T
(DADR = H'0401
to H'FFFD)
1. Always low/high
output (DADR =
H'0003 to H'00FF)
2. (Data value) × T
(DADR = H'0103
to H'FFFF)
1310.72/
1. Always low/high
763 Hz
output (DADR =
H'0001 to H'03FD)
2. (Data value) × T
(DADR = H'0401
to H'FFFD)
1. Always low/high
output (DADR =
H'0003 to H'00FF)
2. (Data value) × T
(DADR = H'0103
to H'FFFF)
41.943/
1. Always low/high
23.84 Hz
output (DADR =
H'0001 to H'03FD)
2. (Data value) × T
(DADR = H'0401
to H'FFFD)
1. Always low/high
output (DADR =
H'0003 to H'00FF)
2. (Data value) × T
(DADR = H'0103
to H'FFFF)
83.886/
1. Always low/high
11.92 Hz
output (DADR =
H'0001 to H'03FD)
2. (Data value) × T
(DADR = H'0401
to H'FFFD)
1. Always low/high
output (DADR =
H'0003 to H'00FF)
2. (Data value) × T
(DADR = H'0103
to H'FFFF)
Fixed DADR Bits
Conversion
Conversion
Bit Data
Accuracy
3
2
1
0
(Bits)
14
12
0
0
10
0
0
0
0
14
12
0
0
10
0
0
0
0
14
12
0
0
10
0
0
0
0
14
12
0
0
10
0
0
0
0
14
12
0
0
10
0
0
0
0
14
12
0
0
10
0
0
0
0
14
12
0
0
10
0
0
0
0
14
12
0
0
10
0
0
0
0
Cycle *
(µs)
655.36
163.84
40.96
655.36
163.84
40.96
1310.72
327.68
81.92
1310.72
327.68
81.92
41.943
10.486
2.621
41.943
10.486
2.621
83.886
20.972
5.243
83.886
20.972
5.243
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