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Section 24 ROM
Write pulse application subroutine
Sub-Routine Write Pulse
WDT enable
Set PSU bit in FLMCR2
Wait (γ) µs
Set P bit in FLMCR1
Wait (z1) µs, (z2) µs or (z3) µs
Clear P bit in FLMCR1
Wait (α) µs
Clear PSU bit in FLMCR2
Wait (β) µs
Disable WDT
End Sub
*
6
Note 7: Write Pulse Width
Write Time (z) µs
Number of Writes n
1
2
3
4
5
6
7
8
9
10
11
12
13
998
999
1000
Note: Use a z3 µs write pulse for additional programming.
RAM
Program data storage
area (128 bytes)
Reprogram data storage
area (128 bytes)
Additional-programming
data storage area
(128 bytes)
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written
to must be H'00 or H'80. A 128-byte data transfer must be performed even if writing
fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
2. Verify data is read in 16-bit (word) units.
3. Even bits for which programming has been completed will be subjected to programming
once again if the result of the subsequent verify operation is NG.
4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional data must be provided in RAM.
The contents of the reprogram data area and additional data area are modified as programming proceeds.
5. A write pulse of z1 µs or z2 µs is applied according to the progress of the programming operation. See Note7 for details of the pulse widths. When writing of
additional-programming data is executed, a z3 µs write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.
6. The values of x, y, z1, z2, z3, α, β, γ, ε, η, θ, and N are shown in section 29.6, Flash Memory Characteristics.
Reprogram Data Computation Table
Original Data
Verify Data
Reprogram Data
(D)
(V)
0
0
0
1
1
0
1
1
Rev. 3.00 Jan 25, 2006 page 734 of 872
REJ09B0286-0300
*
6
6
*
*
5
*
6
*
6
Increment address
z1
z1
z1
z1
z1
z1
z2
z2
z2
z2
z2
z2
z2
z2
z2
z2
Comments
(X)
1
Programming completed
0
Programming incomplete; reprogram
1
1
Still in erased state; no action
Figure 24.9 Program/Program-Verify Flowchart
Start of programming
START
Set SWE bit in FLMCR1
Wait (x) µs
Store 128-byte program data in program
data area and reprogram data area
n = 1
m = 0
Write 128-byte data in RAM reprogram
data area consecutively to flash memory
Sub-Routine-Call
Apply write pulse z1 µs or z2 µs
Set PV bit in FLMCR1
Wait (γ) µs
H'FF dummy write to verify address
Wait (ε) µs
Read verify data
Write data =
verify data?
OK
NG
6 ≥ n ?
OK
Additional-programming data computation
Transfer additional-programming data to
additional-programming data area
Reprogram data computation
Transfer reprogram data to reprogram data area
128-byte
data verification completed?
NG
OK
Clear PV bit in FLMCR1
Wait (η) µs
NG
6 ≥ n?
OK
Successively write 128-byte data from additional-
programming data area in RAM to flash memory
Apply write pulse (Additional programming) z3 µs
NG
m = 0 ?
OK
Clear SWE bit in FLMCR1
Wait (θ) µs
End of programming
Additional-Programming Data Computation Table
Reprogram Data
Verify Data
Additional-
(X')
(V)
Programming Data (Y)
0
0
0
0
1
1
1
0
1
1
1
1
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
*
6
*
4
*
1
*
6
See Note 7 for pulse width
*
6
n ← n + 1
*
6
*
2
NG
m = 1
*
4
*
3
*
4
*
6
*
1
*
3
µs
*
6
NG
n ≥ (N)?
OK
Clear SWE bit in FLMCR1
Wait (θ) µs
*
6
Programming failure
Comments
Additional programming to be executed
Additional programming not to be executed
Additional programming not to be executed
*
6
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