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Section 17 I
2
This LSI has an I
C bus interface (IIC) of two channels.
2
The I
C bus interface conforms to and provides a subset of the Philips I
interface functions. Note however that the register configuration that controls the I
partly from the Philips configuration.
17.1
Features
2
• Selection of I
C bus format or clocked synchronous serial format
2
I
C bus format: Addressing format with acknowledge bit, for master/slave operation
Clocked synchronous serial format: Non-addressing format without acknowledge bit, for
master operation only
2
• For I
C bus format, two ways of setting slave address
• For I
2
C bus format, start and stop conditions generated automatically in master mode
2
• For I
C bus format, selection of acknowledge output levels when receiving
• For I
2
C bus format, automatic loading of acknowledge bit when transmitting
2
• For I
C bus format, wait bit function in master mode
A wait can be inserted by driving the SCL pin low after data transfer, excluding
acknowledgement.
The wait can be cleared by clearing the interrupt flag.
• For I
2
C bus format, wait function is available
A wait request can be generated by driving the SCL pin low after data transfer, excluding
acknowledgement.
The wait request is cleared when the next transfer becomes possible.
• Interrupt sources
Data transfer end (including when a transition to transmit mode with I
when ICDR data is transferred, or during a wait state)
Address match: When any slave address matches or the general call address is received in
slave receive mode with I
arbitration)
Arbitration loss
Start condition detection (in master mode)
Stop condition detection (in slave mode)
• Selection of 16 internal clocks (in master mode)
IFIIC50A_000020020300
2
C Bus Interface (IIC)
2
C bus format (including address reception after loss of master
2
Section 17 I
C Bus Interface (IIC)
2
C bus (inter-IC bus)
2
C bus format occurs,
Rev. 3.00 Jan 25, 2006 page 473 of 872
2
C bus differs
REJ09B0286-0300
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