Usage Notes; Note On Resonator; Notes On Board Design; Figure 26.8 Note On Board Design Of Oscillation Circuit Section - Renesas H8S/2158 User Manual

Section 26 Clock Pulse Generator
of the PLL circuit output clock. For details, see section 18.3.17, USB PLL Control Register
(UPLLCR).
The 24-MHz clock generated by the PLL circuit can also be used as the system clock. For details,
see section 27.1.3, System Control Register 2 (SYSCR2).
To activate the PLL circuit, first clear the SMSTPB1 bit in SUBMSTPBL to 0, then after clearing
the USB module stop mode, make settings for UPLLCR. If the USB module is not used, after
activating the PLL circuit, set the SMSTPB1 bit in SUBMSTPBL to 1 to make the USB module
enter module stop mode.
26.9

Usage Notes

26.9.1

Note on Resonator

Since all kinds of characteristics of the resonator are closely related to the board design by the
user, use the example of resonator connection in this document for only reference; be sure to use
an resonator that has been sufficiently evaluated by the user. Consult with the resonator
manufacturer about the resonator circuit ratings which vary depending on the stray capacitances of
the resonator and installation circuit. Make sure the voltage applied to the oscillation pins do not
exceed the maximum rating.
26.9.2

Notes on Board Design

When using a crystal resonator, the crystal resonator and its load capacitors should be placed as
close as possible to the EXTAL and XTAL pins. Other signal lines should be routed away from
the oscillation circuit to prevent inductive interference with the correct oscillation as shown in
figure 26.8.

Figure 26.8 Note on Board Design of Oscillation Circuit Section

Rev. 3.00 Jan 25, 2006 page 768 of 872
REJ09B0286-0300
Prohibited Signal A Signal B
C
L2
C
L1
This LSI
XTAL
EXTAL